1. Field of the Invention
The present invention generally relates to clock-and-data recovery systems where a periodic clock signal is to be extracted from non-periodic data, and the same clock is then used to sample data with a minimum of errors.
2. Description of the Related Art
Phase-locked loop circuits play a critical role in high speed data communications. They are used in clock-and-data recovery circuits, in which clock and data are recovered from a single high-speed serial stream of non-return-to-zero data. Ethernet, Fibre Channel, and SONET/SDH transmission systems are specific examples of systems that typically use phase-locked loop-based clock-and-data recovery circuits.
FIG. 1 shows a block diagram of a conventional phase-locked loop-based clock-and-data recovery 10, which has a phase detector 12, a loop filter 14, and a voltage-controlled oscillator 16. The phase-locked loop-based clock-and-data recovers circuit 10 is connected to a D-type flip-flop 18. The phase detector 12 receives the clock data stream and the clock signal from the voltage-controlled oscillator 16, and compares the timing difference between the data transition in the data stream and the clock edge from the voltage-controlled oscillator 16. The phase detector 12 then generates an error voltage to tune the voltage-controlled oscillator frequency.
Conventional phase detectors 12 are usually also accompanied by a charge pump (not shown) in modern integrated circuit design. The loop filter 14 between the phase detector 12 and the voltage-controlled oscillator 16 rejects high frequency noise that is embedded in the incoming data.
The feedback operation shown in FIG. 1 forces the clock edge from the voltage-controlled oscillator to be aligned to the data transition in steady state, and the D-type flip-flop 18 samples the data with the recovered clock signal. To reduce the bit-error rate of the communications link, the data should be retimed in such a way that the clock edge that is used to sample data is aligned to the middle of the data bit period.
In clock-and-data recovery systems, noise is an overriding design concern. For a phase-locked loop, noise is quantified by measuring the jitter of the phase-locked loop output. For example, for SONET applications, the jitter transfer function is important and is required to have less than a 0.1 dB peaking at 3 dB corner frequency. Jitter peaking should be avoided when a phase-locked loop is used repeatedly, as in a SONET application, since it amplifies jitter at a certain frequency band where peaking occurs in jitter transfer function. The peaking at the 3 dB corner frequency usually happens if the loop dynamic of the phase-locked loop is not well designed, which is one of the reasons that prevent phase-locked loop bandwidth from being widened. Thus, to design a low-jitter phase-locked loop is challenging in many ways due to stringent jitter budgets and loop bandwidth specifications. The phase-locked loop in a clock-and-data recovery circuit provides three functions: (a) it filters out noise in the data channel: (b) it extracts clock information: and (c) it tracks the jitter of the data for better data retiming. Having the data sampled by a single D-type flip-flop, conventional phase-locked-loop based clock-and-data recovery circuits provide instant data retiming with the recovered clock signal.
To accommodate high-frequency timing variation of the data edge, the phase-locked loop needs to exhibit an agile response to track the short-term jitter using wide loop bandwidth. However, wide loop bandwidth can limit the noise-filtering from the data channel as the noise bandwidth increases. As the clock is perturbed by unwanted channel noise, the bit-error rate will increase simply due to the clock itself Therefore, there is a fundamental tradeoff in choosing loop bandwidth between the clock extraction and the data retiming.